1. Field of the Invention
The invention relates in general to the method of forming semiconductor circuits (ICs), and more particularly to a method of forming borderless contacts.
2. Description of the Related Art
The line width of a metal oxide semiconductor (MOS) becomes smaller and smaller when device integration increases. A metal line is used to contact the source/drain region of the MOS. Since the size of the source/drain region is smaller than the metal line or misalignment occurs between the source/drain region and the metal line, a part of the metal line contacts a shallow trench isolation structure (STI). According the result described above, a borderless contact process is provided to ensure the insulating effect of the STI without decreasing the device integration.
FIGS. 1A to 1D are schematic, cross-sectional views showing the progression of manufacturing steps in producing a borderless contact according to a conventional method.
In FIG. 1A, a substrate 100 is provided. The substrate 100 has at least a MOS transistor and STI structures 102 near the MOS transistor thereon. The MOS transistor comprises a gate 107, a spacer 108, a source region 104 and a drain region 106. The gate 107 comprises a salicide layer 112, a polysilicon layer 110 and a gate oxide layer 113. A titanium silicide layer 109 is formed on the source region 104 and the drain region 106. A silicon nitride layer 114 is formed over the substrate 100 to cover the MOS transistor and the STI structures 102. A dielectric layer 116 is formed on the silicon nitride layer 114.
In FIG. 1B, a defined photoresist layer 118 is formed on the dielectric layer 116. The photoresist layer 118 has a first opening 115 exposing the drain region 106, a second opening 117 exposing the gate 107 and a third opening 119 exposing the source region 104.
In FIG. 1C, a part of the dielectric layer 116 is removed until the silicon nitride layer 114 is exposed using the photoresist layer as a mask layer. A fourth opening 121, a fifth opening 123 and a sixth opening 125 are thus formed in the dielectric layer 116.
In FIG. 1D, the exposed silicon nitride layer 14 is removed to form a first contact window 120 to expose the source region 106, to form a second contact window 122 to expose the gate 107, and to form a third contact window 124 to expose the drain region 104. The photoresist layer 118 is removed. A part of the third contact window 124 exposes the STI structure 102.
In the conventional method described above, the MOS transistor is used to form logic devices. A part of the silicon nitride layer 114 over the gate has the same thickness as another part of the silicon nitride layer 114 over the source/drain region so that an etching step for forming the contact windows requires only one mask. However, an embedded dynamic random access memory (DRAM) comprises a logic region and a memory cell region. A gate in the logic region comprises a cap layer, a polycide layer, a polysilicon layer and a gate oxide layer. The silicon nitride layer on the gate is thicker than the silicon nitride layer on the source/drain region. In the logic region of the embedded DRAM, using one mask for forming contact windows exposing the gate and the source/drain region is very difficult.